1. Field of the Invention
The present invention relates to a semiconductor device having a trench interconnection, and a method of manufacturing the semiconductor device.
2. Description of the Related Art
It is essential in recent VLSI devices, to miniaturize and multilayer elements, since millions of elements need to be integrated on a chip with a few square millimeters. In particular, it is important to reduce interconnection resistance and interlayer capacitance, in order to increase a device operating speed.
To reduce the interconnection resistance and the interlayer capacitance, a method is employed that uses copper as an interconnection material and a film having a dielectric constant lower than that of a silicon oxide film as an interlayer dielectric film. Further, a dual-damascene method is used to reduce the number of processes and to improve reliability of a copper interconnection. In the dual-damascene method, since a copper embedding process and a copper CMP process can be cut compared with a single-damascene method, the processes can be greatly reduced. Further, in the dual-damascene method, copper is embedded in an interconnection trench and a via hole at one time. Therefore, breaking of the copper interconnection due to electromigration is not caused, and the reliability of the copper interconnection is improved. There are two conventional techniques for the dual-damascene method.
The first conventional technique is a method of forming a dual-damascene interconnection configuration, generally referred to as a via first method. The technique is disclosed in, for example, T. I. Bao, et al., “90 nm Generation Cu/CVD Low-k (k<2.5) Interconnect Technology”, IEEE International Electron Device Meeting (IEDM) 2002, pp 583.
FIGS. 1A to 1G are views showing a method (via first method) of manufacturing a dual-damascene interconnection configuration of the first conventional technique. In each of Figures, the upper part is a top view, and the lower part is an AA cross-sectional view of the top view.
First, as shown in FIG. 1A, a cap film 102 is formed on an upper surface of a lower interconnection layer 101. The cap film 102 is an etching stopper in etching a via interlayer film 103. The via interlayer film 103 is formed on an upper surface of the cap film 102. A stopper film 104 is formed on an upper surface of the via interlayer film 103. The stopper film 104 is an etching stopper in etching a trench interlayer film 105. The trench interlayer film 105 is formed on an upper surface of the stopper film 104. A hard mask 106 is formed on an upper surface of the trench interlayer film 105. An antireflection film 108 and a photoresist 109 are formed on an upper surface of the hard mask 106. A resist pattern 109a for a via-hole opening is formed to the photoresist 109 by using a photolithography technique. Here, a case is shown where the resist pattern 109a is out of alignment by Δd1 from a lower interconnection of the lower interconnection layer 101.
Next, as shown in FIG. 1B, the antireflection film 108, the hard mask 106, the trench interlayer film 105, the stopper film 104, and the via interlayer film 103 are etched in order, by using the photoresist 109 on which the resist pattern 109a is formed, as a mask. As a result, a via-hole pattern 103a is formed. At this time, etching of the via interlayer film 103 stops at the cap film 102.
Subsequently, as shown in FIG. 1C, the resist 109 and the antireflection film 108 are removed. After that, as shown in FIG. 1D, an antireflection film 110 and a photoresist 111 are formed on the upper surface of the hard mask 106. The antireflection film 110 protects the cap film 102 under the via-hole pattern 103a. Further, a resist pattern 111a for the interconnection trench is formed to the photoresist 111 by using the photolithography technique. At this time, the resist pattern 111a is exposed in alignment with the via-hole pattern 103a. Here, a case is shown where the resist pattern 111a is out of alignment by Δd2 from the via-hole pattern 103a in the photolithography process.
Next, as shown in FIG. 1E, the antireflection film 110, the hard mask 106, and the trench interlayer film 105, which are under the trench of the resist pattern 111a, are etched in order. As a result, an interconnection trench pattern 105a is formed. The cap film 102 under the via-hole pattern 103a is protected from an etching plasma, by an antireflection film under the via-hole pattern 103a. Next, as shown in FIG. 1F, a dual-damascene configuration is formed by removing the cap film 102 after removing the resist 111 and the antireflection film 110.
Next, as shown in FIG. 1G, a barrier film and copper are embedded in the via-hole pattern 103a and the interconnection trench pattern 105a, and a copper interconnection 112 is formed. In this via first method, as shown in the upper part of FIG. 1G, an increase in via resistance corresponds to Δd1 only, even if a via pattern for the lower interconnection is out of alignment by Δd1. In addition, even if an upper interconnection for the via pattern is out of alignment by Δd2, a space between interconnections are narrowed corresponding to Δd2 only, a short circuit then being less likely to happen.
That is, the via first process has a characteristic that a margin can be secured for a misalignment between the via hole (via-hole pattern 103a) and the interconnection trench (interconnection trench pattern 105a), since the via pattern (via-hole pattern 103a) is formed earlier.
In the conventional technique of this via first process, an etching residue may be generated in the vicinity of the via-hole opening. FIG. 2 is a cross-sectional view showing the generation of the etching residue in the conventional technique of the via first process. The residue is mainly an etching product which is adhered to the sidewall of the resist or antireflection film embedded in the via during the trench etching. The etching residue causes the breaking of interconnections and a reduction in the reliability, needing to be restrained. The etching residue is especially likely to be generated when the upper interconnection has a wide width.
Further, in the via first process, there are two times of ashing in the situation that the interlayer films (the via interlayer film 103 and the trench interlayer film 105) are bared (FIGS. 1C and 1F). As a result, when a low dielectric constant film and so on, which is weak for an ashing plasma, is used as the interconnection interlayer film (the trench interlayer film 105), damage caused is significant.
Also, it is extremely difficult in the via first process, to remove the resist and again perform trench exposure after trench formation, due to such causes as poor exposure and misalignment. If the ashing is performed after the trench exposure under the condition that the damage due to nitrogen and hydrogen plasmas and so on is not given to the interlayer film, the hard mask 106 is etched at the edges thereof being rounded. As a result, the interlayer film may be bared.
In addition, there is a problem of via poisoning in the via first process. Since a gas is emitted from the resist embedded in the via hole, a situation may occurs, in which a periphery of the via is not well exposed. Due to this via poisoning, it is possible that a portion where the interconnection trench pattern is supposed to be formed, to be connected to the via hole, is not etched, causing a risk of generating a non-connection portion between the via and the interconnection.
As a second conventional technique, there is a dual hard mask method in which an inorganic film to be a cap of a low dielectric constant film is made into two layers. The technique is disclosed in, for example, R. Kanamura, et al., “Integration of Cu/low-k Dual-Damascene Interconnects with a Porous PAE/SiOC Hybrid Structure for 65 nm-node High Performance eDRAM”, 2003 Symposium on VLSI Technology, pp 107.
FIGS. 3A to 3I show a manufacturing method (dual hard mask method) of a dual-damascene interconnection configuration of the second conventional technique. In each of Figures, the upper part is a top view, and the lower part is an AA cross-sectional view of the top view.
First, as shown in FIG. 3A, a cap film 102, a via interlayer film 103, a stopper film 104 and a trench interlayer film 105 are formed on the upper surface of a lower interconnection layer 101, as in the case of FIG. 1A. After that, a lower hard mask 106, an upper hard mask 107, an antireflection film 108 and a photoresist 109 for an interconnection trench are formed on the upper surface of the trench interlayer film 105. A resist pattern 109a for a via-hole opening is formed to the photoresist 109 by using the photolithography technique. Here, a case is shown where the resist pattern 109a is out of alignment by Δd3 from a lower interconnection of the lower interconnection layer 101 in the photolithography process.
Next, as shown in FIG. 3B, the antireflection film 108 and the upper hard mask 107 are etched by using the resist pattern 109a as a mask, and the lower hard mask 106 as a stopper. As shown in FIG. 3C, resist removal is performed by using an oxygen plasma. An interconnection trench pattern 107a is formed to the upper hard mask 107 by such a process. That is, the dual hard mask method is one kind of a trench first process. After that, as shown in FIG. 3D, an antireflection film 110 is formed on the upper hard mask 107. A photoresist 111 for the via is formed thereon. A via-hole pattern 111a is formed to the photoresist 111. Here, a case is shown where the via-hole pattern 111a is out of alignment by Δd4 from the lower interconnection of the lower interconnection layer 101 in the photolithography process.
Subsequently, as shown in FIG. 3E, the antireflection film 110, the upper hard mask 107, the lower hard mask 106, the trench interlayer film 105, and the stopper film 104 are etched to form a half via-hole pattern 104a by using the photoresist 111 as a mask. After that, as shown in FIG. 3F, the photoresist 111 and the antireflection film 110 on the lower hard mask 106 and the upper hard mask 107 are removed.
Next, as shown in FIG. 3G, the lower hard mask 106 and the trench interlayer film 105 are etched by using the upper hard mask 107 as a mask. At this time, the via interlayer film 103 is etched at the same time in the half via-hole pattern 104a as well by using the stopper film 104 as a mask. By removing the cap film 102 and the stopper film 104, the dual-damascene configuration is formed. Finally, as shown in FIG. 3H, a copper interconnection is formed by embedding a barrier metal and copper in the half via-hole pattern 104a and the interconnection trench pattern 107a. 
In the dual hard mask method, the resist and the antireflection film are not embedded in the via hole, since a trench pattern is printed on an inorganic film of the upper hard mask 107. For this reason, an ashing process for removing the resist and the antireflection film in the via hole is not included, and excessive damage is not caused to the low dielectric constant films (the via interlayer film 103 and the trench interlayer film 105) on an interconnection trench sidewall and a via hole sidewall. Further, even if misalignment occurs to a via pattern of the photoresist at the time of via exposure for the interconnection trench pattern 107a of the upper hard mask 107, oxygen ashing can be performed to the photoresist without causing the low dielectric constant film to come in contact with a plasma. Consequently, a via exposure process can be repeated until the misalignment comes equal to or below a desired value.
The conventional technique of the dual hard mask method has many superior aspects to the first conventional technique of the via first method, in terms of damage reduction to the low dielectric constant film, and the avoidance of the via poisoning.
However, in the dual hard mask method, the misalignment trouble occurs, caused by the trench first process for forming the trench pattern firstly to the upper mask.
Details thereof are explained with reference to FIGS. 3A to 3I. In FIG. 3A, the interconnection trench pattern (the resist pattern 109a) is out of alignment by ΔD3 from the lower interconnection of the lower interconnection layer 101. On the other hand, in FIG. 3D, the via-hole pattern 111a is out of alignment by ΔD4 in an opposite direction from the lower interconnection mentioned above. As a result, as shown in FIG. 3H, the via hole is out of alignment by ΔD3+ΔD4 from the upper interconnection. Therefore, in the case of a dense pitch interconnection, the via and the interconnection come close to each other, causing a risk of the short circuit.
Also, another problem is caused when the via-hole pattern formation in FIG. 3D is performed for the interconnection trench pattern 107a in order to avoid the risk of the short circuit. In this case, the via hole may be out of alignment by ΔD3+ΔD4 from the lower interconnection. Therefore, it is expected that a via contact portion is reduced and the via resistance is increased, like a P region in FIG. 3I.
Thus, when using the dual hard mask method, it is impossible to avoid both the short circuit and the increase in the via resistance, even if via alignment is performed for the lower interconnection of the lower interconnection layer 101 and the hard mask pattern (the interconnection trench pattern 107a) for the interconnection trench formation. This is caused by the fact that the dual hard mask method is originally the trench first process, and cannot be avoided.
Further, also in the dual hard mask method, the interlayer film (the trench interlayer film 105) is bared at the time of the ashing after the via formation of FIG. 3E, and the ashing damage at this time cannot be avoided.
Thus, a focus on a multilayer interconnection configuration reveals that the problems of the etching residue and the ashing damage are caused in the via first method of the first conventional technique. In the dual hard mask method of the second conventional technique, the problem of the misalignment is caused. Technique is desired that forms a multilayer interconnection configuration having less damage to a low dielectric constant film. A technique is desired that can avoid problems caused by the misalignment such as the short circuit and the increase in the via resistance. Further, a technique is desired that can form a multilayer interconnection configuration superior in a via manufacturing yield.
In conjunction with the above description, a method of manufacturing a semiconductor device and the semiconductor device are disclosed in Japanese Laid Open Patent Application JP-P2002-43419A. This is a method of manufacturing a semiconductor device in which a first interconnection and a second interconnection thereon are formed on a semiconductor substrate, and a through hole is formed between the first and second interconnections. An insulating film deposition process, a deposition process of a multilayer hard mask layer, a first opening forming process, a second opening forming process, a third opening forming process, and an interconnection trench for the second-interconnection/the through hole forming process, are included.
The insulating film deposition process forms in order as an interlayer films on the first interconnection, a first insulating film functioning as an anti-diffusion film of interconnection metal of the first interconnection, and a second insulating film that includes a low dielectric constant film layer, when forming the second interconnection and the through hole. The deposition process of a multilayer hard mask layer includes an insulating hard mask layer of at least three layers formed on the second insulating film, where the three layers as the insulating hard mask layer is a multilayer hard mask layer of which etching rate is different from each other under the same etching condition. Then, a first insulating hard mask layer, a second insulating hard mask layer, and a third insulating hard mask layer are formed in order, on the second insulating film. The first opening forming process etches the third and the second hard mask layers to form the first opening, which is a through hole pattern, on the first hard mask through self-alignment. The second opening forming process etches the third hard mask layer to form the second opening connected to the first opening on the second hard mask layer. Here, the second opening is the interconnection trench pattern of the second interconnection. The third opening forming process has a step of etching the first hard mask layer and a step of etching the second insulating film, by using the second hard mask layer as an etching mask to form a third opening connected to the first and second openings for baring the first insulating layer. The interconnection trench for the second-interconnection/the through hole forming process etches the upper parts of the second hard mask layer, the first hard mask layer and the second insulating film by using the third hard mask layer as the etching mask to form the interconnection trench for the second interconnection, and etches the first insulating layer to open a through hole for baring the first interconnection.
In the insulating film deposition process, a first low dielectric constant layer, an electrically insulating etching stopper layer having the same composition as that of the second hard mask layer and a second low dielectric constant layer may be formed in order, with respect to the second insulating film that includes a low dielectric constant layer. The third opening forming process may have a step of etching the first hard mask layer to bare the second low dielectric constant layer by using the second hard mask layer as an etching mask, a step of etching the second low dielectric constant layer to bare the etching stopper layer, and a step of etching the etching stopper layer. In the interconnection trench/through hole forming process, the second hard mask layer, the first hard mask layer, and the second low dielectric constant layer may be etched by using the third hard mask layer as an etching mask to bare the etching stopper layer and form the interconnection trench of the second interconnection. Further, the first insulating film may be etched to open a through hole for baring the first interconnection.
In conjunction with the above description, a method of manufacturing a semiconductor device is disclosed in Japanese Laid Open Patent Application JP-P2002-64139A. The manufacturing method of the semiconductor device forms an interconnection of a dual-damascene configuration. The manufacturing method includes (a) a process of embedding a first barrier layer and a lower interconnection in a first trench pattern formed to a first insulating layer on a substrate, (b) a process of forming a second insulating layer to an upper layer of the lower interconnection, (c) a process of forming a second trench pattern on an upper part of the second insulating layer by etching using a first resist pattern as a mask, (d) a process of forming a hole pattern that reaches the first barrier layer, to a lower part of the second insulating layer and to the lower interconnection by etching using a second resist pattern as a mask, and (e) a process of embedding a second barrier layer and an upper interconnection in the second trench pattern and the hole pattern.
In conjunction with the above description, a semiconductor device and a method of manufacturing the same are disclosed in Japanese Laid Open Patent Application JP-P2003-45964A. The semiconductor device includes an interlayer insulating film formed to cover a lower interconnection; and a via plug and an upper interconnection formed at the same time to a via hole and an interconnection trench respectively, which are formed to the interlayer insulating film; wherein the lower interconnection is connected with the upper interconnection through the via plug. The interlayer insulating film is formed by an insulating film of a low dielectric constant, and is covered with a hard mask. The interlayer insulating film may be formed by an organic layer.
In conjunction with the above description, a semiconductor device and a manufacturing method of the same are disclosed in Japanese Laid Open Patent Application JP-P2003-133411A. In the semiconductor device, an interlayer insulating film on a substrate in which semiconductor elements are formed includes a first organic insulating film; a first insulating film, which is different from the organic insulating film, formed on the first organic insulating film; a second organic insulating film formed on the first insulating film; and a second insulating film, which is different from the organic insulating film, formed on the second organic insulating film. The semiconductor device has an interconnection trench formed to the second insulating film and a part of the second organic insulating film at least, and has a contact hole that is at least connected to the bottom of the interconnection trench, formed across the first insulating film and the first organic insulating film. A third organic insulating film may be formed on the second insulating film, and the interconnection trench may be formed across the third organic insulating film, the second insulating film, and at least a part of the second organic insulating film.
In conjunction with the above description, an interconnection configuration and a method of manufacturing the same are disclosed in Japanese Laid Open Patent Application JP-P2003-163265A. A configuration of a trench interconnection formed to an insulating film on a semiconductor substrate is disclosed. A trench interconnection having a minimum line width in one interconnection layer, is connected to a lower interconnection through a via hole having the same value of a bore diameter as that of the minimum line width. A trench interconnection having the minimum line width or above in the interconnection layer, is connected to the lower interconnection through a via hole having a value of a bore diameter larger than that of the minimum line width.